Bus interfaces and/or connecting methods are available, e.g., for a controller area network bus (CAN bus) in motor vehicles. Such a bus has a pair of bus lines, wherein one bus line has a signal level with a time characteristic that is complementary to that of the other bus line. The bus interfaces are used for coupling of bus devices in phase opposition, e.g., communication components, systems and/or subsystems, to the bus. A bus interface having a pair of driver circuits is known, wherein a first driver circuit with an output is connected to the first bus line and a second driver circuit which is complementary in operation to the first driver circuit which has an output that is connected to the second bus line. Each driver circuit has a switching element, one being implemented as a p-channel transistor and the other being implemented as an n-channel transistor.
In the case of such a bus interface, the inputs of both driver circuits are connected to the bus device. Triggering of the two driver circuits in phase opposition is accomplished with an inverting element at one of the two inputs. However, the triggering of the two driver circuits in phase opposition thus embodied results in phase displacement and asymmetry between the output signals of the two driver circuits because of differences in transit time, differences in the p- and n-channel transistors used and/or component tolerances. Consequently, there is the risk that the output signals are not sufficiently accurately in phase opposition, which results in increased high-frequency emission to the outputs and the bus lines.
U.S. Pat. No. 6,111,431 relates to a driver circuit for transmitting a differential signal to an external circuit. According to this embodiment, the driver circuit has a plurality of transistors P21, P22 and P33. In the event of an output-end short circuit to the driver circuit, damage to transistors N21, N22 is prevented by a component R31. Transistors N11 and N12 are protected from a short circuit in the driver circuit in a similar manner. Transistors P21 and P22 are controlled by a first operational amplifier OPAMP1, while transistors N11 and N12 are controlled by a second operational amplifier OPAMP2. Transistors N22, N23 and transistors N21, N24 are alternately turned on and off by the arrangement of two inverters IV31, IV34 and NOR gates 31, 34 and NOR gates 32, 33.